1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for forming a dual interlayer dielectric layer capable of preventing an interlayer delamination phenomenon generated between an etch stop layer and an interlayer dielectric layer.
2. Description of the Related Art
As the current trend in semiconductor devices change toward high integration and smaller sizes, a borderless contact (BLC) technique has been suggested in order to assure a margin capable of compensating for a misalignment in a contact process. Such a technique refers to a method in which a contact is self-aligned by means of a sidewall spacer of a gate when the contact is formed inside the interlayer dielectric layer (ILD) so as to connect with a source/drain region of a silicon substrate. Thus, the borderless contact technique is referred to as a self-aligned contact (SAC) method.
However, such a contact may partially overlap an isolation layer due to mask misalignment. Therefore, the borderless contact technique typically requires an etch stop layer in order to protect an isolation layer in an anisotropic plasma etching process forming a contact hole. This is because the isolation layer may be physically damaged by the contact hole etching process which causes a leakage current, thereby deteriorating the qualities of the semiconductor device.
FIG. 1 is a cross-sectional view showing a structure of an interlayer dielectric layer of a semiconductor device according to the related art.
As shown in FIG. 1, a gate insulating layer 12 and a gate 13 are formed on a silicon substrate 10 including an isolation layer 11. A sidewall spacer 14 is formed on both sidewalls of gate 13, respectively, and a source/drain region 15 is formed in silicon substrate 10. A silicide (not shown) is formed on source/drain region 15 and gate 13, respectively. Etch stop layer 16 is formed in such a manner as to cover the entire structure, and an interlayer dielectric layer 17 is sequentially formed on etch stop layer 16. A contact hole is formed by etching interlayer dielectric layer 17, and then a conductive material (e.g., tungsten) is deposited in the contact hole, thereby forming a contact 18.
In such a conventional structure, etch stop layer 16 is made of silicon nitride, and interlayer dielectric layer 17 includes an oxide layer formed using high-density plasma chemical vapor deposition (hereinafter, refers to as a “HDP-CVD”) having superior gap fill capacity. However, an interlayer delamination phenomenon is frequently generated since the adhesion force between etch stop layer 16 and interlayer dielectric layer 17 is weak. Further, compressive stress of etch stop layer 16 and interlayer dielectric layer 17 stacked on etch stop layer 16 accumulates, causing the interlayer delamination phenomenon. When such interlayer delamination phenomenon is generated, the contact material penetrates into the etched region during the subsequent process, i.e., a contact material deposition process, causing an electric short and deteriorating the product yield of the semiconductor device.